There has been an increasing demand for higher power and a higher withstand voltage in power semiconductor devices in which power semiconductor elements such as a MOS-FET and an IGBT are mounted. Various semiconductor elements and packages for the semiconductor elements have been proposed in response to the demand.
In a semiconductor device of the prior art, a semiconductor element and an external terminal are bonded via a belt of Al (aluminum ribbon) by wedge bonding to reduce an on resistance at the joint of the terminal, so that an electric resistance at the joint is reduced. In another semiconductor device of the prior art, an on resistance is further reduced by providing a large number of joints on the source electrode of a semiconductor element to be subjected to wedge bonding.
FIGS. 3(a) and 3(b) are an explanatory drawing showing the configuration of a semiconductor device of the prior art. FIG. 3(a) is a plan view showing the internal configuration of the MOS-FET of a power semiconductor device that is a semiconductor device of the prior art described in Patent Literature 1. FIG. 3(b) is a sectional view taken along line X-X′ of FIG. 3(a).
FIGS. 3(a) and 3(b) show a power semiconductor device 101 including the MOS-FET mounted as a semiconductor element 103 on a lead frame 102. On the major surface of the semiconductor element 103, a source electrode 103a and a gate electrode 103b are formed. The source electrode 103a and the gate electrode 103b are made up of conductive films, mainly Al films. The source electrode 103a is configured with a larger area than the gate electrode 103b to reduce an on resistance. Further, a drain electrode 103c is formed over the opposite surface of the semiconductor element 103 from the major surface. The drain electrode 103c is bonded to a die pad 102a of the lead frame 102 via conductive paste 104 such as Ag paste. The gate electrode 103b is connected to a gate terminal 102c, which has a bonded region extended on the end of a lead of the lead frame 102, via a conductive wire 105 such as an Au wire. The source electrode 103a is connected to a source terminal 102b, which has a bonded region formed by combining the multiple leads 102, via a conductive ribbon 106. The gate terminal 102c and the source terminal 102b have regions bonded to the conductive wire 105 and conductive ribbon 106, respectively. These regions are normally equal in length in the horizontal direction of FIGS. 3(a) and 3(b) (in parallel with a side of the conductive ribbon 106 from the source electrode 103a to the source terminal 102b, hereinafter will be called the longitudinal direction of the conductive ribbon). In many cases, these regions are about 0.5 mm in length. The conductive ribbon 106 is wedge bonded by a wedge tool. Multiple joints 108 called stitches are formed on the source electrode 103a, and then the conductive ribbon 106 is connected to the source terminal 102b according to the same bonding rule, so that the bonded area is increased so as to reduce the on resistance of the source electrode 103a (e.g., see Patent Literature 1).
For example, when the chip size of the semiconductor element 103 is about 2 mm×3 mm, the size of the source electrode 103a is 1.5 mm×2.8 mm, and an aluminum ribbon serving as the conductive ribbon 106 has a width of 1.5 mm and a thickness of 0.1 mm, the on resistance can be reduced by about 20% to 30% by forming two identical joints as compared with the case where a single joint is formed with a width of 0.2 mm to 0.3 mm in the longitudinal direction of the conductive ribbon.
Citation List
Patent Literature
    Patent Literature 1: Japanese Patent Laid-Open No. 2004-336043